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Automation has been a part of chip design since the 1980s. But now AI-designed chips are producing great results that could lead to 1,000 times better performance for chips in the next decade, according to Synopsys CEO Aart de Geus.
De Geus, one of the pioneers of chip design automation, said in an interview with VentureBeat that the company’s software started using AI to design customer chips last year, with considerable improvements over human-designed chip architects. Rival Cadence Design Systems launched its own AI effort this year. But rather than making chip architects obsolete, De Geus believes this will move them up the chain and they will become responsible for more kinds of tasks than is possible today.
“About 3% of designers said ‘Now you’re taking my job away’ back then,” he said. “But 97% have said ‘This is great.’ Now I can do more things much faster. And I think we’re going to see exactly the same with design software automation (DSO), which is so powerful that it can look at (and understand) things that the human can no longer see.”
De Geus will talk about the AI approach to chip design at the Hot Chips online chip conference today. De Geus said he believes Synopsys and AI will play a critical role in helping the chip industry achieve a 1,000-times performance increase in the next decade, helping it stay on the path of Moore’s Law (doubling chip performance every couple of years) even after scaling through manufacturing advances hits its limits.
“We’re going to deliver 1,000 times performance at the end of the decade,” he said. “I have high confidence about that. I think we have had the end of classic Moore’s Law. And I believe this new era is moving from scale complexity to systemic complexity. I think the ambition is very high.”
Origins of design automation
Above: Chip design through the ages: Now it’s AI’s turn.
De Geus started Synopsys as an electronic design automation (EDA) software company in 1986. Last year, the company posted $3.69 billion in revenues. It started out with a kind of AI that was more like translation software. Synopsys’ logic synthesis takes a design for a chip in the form of abstract specification of its logic circuits, typically at register transfer level (RTL), and turns it into a design implementation in terms of logic gates. That can in turn be converted into the physical layout for the surface of a chip. This design then goes to manufacturing.
De Geus noted that 35 years ago, logic synthesis helped launch the digital age and its exponential growth. At Synopsys, which will mark over 35 years in December, the EDA industry will have delivered 10 million times improvements in chip design productivity.
Synopsys now takes a comprehensive approach to autonomous chip design — going beyond just layout. It leverages reinforcement learning to simultaneously optimize for power, performance, and area. Power refers to how much voltage it takes to power a chip. Performance measures the calculations it can do in a given time. And area refers to the size of the chip. The latter is important for keeping chip costs low.
Applying AI to address complexity, power, and scaling requirements to reach the 1,000 times performance target is critical to moving beyond Moore’s Law, which relied on manufacturing advances for productivity improvements in the past. As those manufacturing improvements hit limits because miniaturization is now at the atomic level, other kinds of improvements in design have to happen.
Above: Automation is different in the new age of chip design.
De Geus said the company’s efforts to automate design have always aimed for quality of results, time to results, and cost of results.
Synopsys released the first incarnation of its AI design software as DSO.ai in 2020. It’s now being used in production environments with real customers and is enhanced to provide more complete system-level optimization. Customers include Cerebras, which makes a single chip out of an entire wafer (which normally can be divided into hundreds of chips). Cerebras’ second-generation chip has 2.6 trillion transistors, the on-off switches of digital computing.
“Machine learning is now used on every one of our tools,” de Geus said. “What is different about this new tool, which we call design space optimization (DSO), is that it doesn’t apply to individual design steps, but to a whole design flow.”
It also addresses rapid customization of chips for specific applications, as well as all dimensions of systems: hardware (physics), software (function), manufacturability, and architecture (form).
Above: Synopsys sees a path to 1,000 times better performance in a decade.
“And what that really means is that the optimizations get done by looking at the much more complex search space than any individual tool would,” he said. “We started to see great results about 18 months ago because at that point in time, we could duplicate, not identically, but duplicate in terms of results. What took humans typically multiple months could now be done in a matter of weeks. And so that was about 18 months ago, and then about six months later, we systematically started to get better results.”
AI can assist humans in figuring out exactly what to create and increasing the number of iterations a design can go through before it’s complete.
“We are now touching some of the decisions that will be difficult for a designer to evaluate because it just takes too much time,” de Geus said. “And the results still improved substantially. And so we’re in a situation now where we have many designers using this on real designs. Quite a number of those have [hit final design], and some have now come back for manufacturing.”
De Geus refers to this kind of design as an artificial architect, but human chip designers and architects probably don’t like that term, as it suggests humans are no longer necessary in chip design, he acknowledged. But de Geus sees humans moving up the chain as AI takes over more mundane tasks. He sees engineers moving up, in that each engineer used to be responsible for designing a small number of transistors. Now an engineer might be in charge of a billion transistors in a larger chip.
Better AI results
Above: AI is getting better at chip design than humans.
In early adoptions by customers, Synopsys’ tools have demonstrated their ability to reduce power by 25% compared to a world-class design team using state-of-the-art design tools. That’s 5 times the power savings the best AI-design tools deliver today. And it is roughly the same as the power reduction from shifting forward one to two process nodes, but done entirely by software.
De Geus noted that in 2018 the amount of data used in designs crossed over from human-generated to machine-generated.
“And now machine generation has become way bigger,” he said. “The question is, can we get something better? And the answer, of course, is that we can get to 10 times, 100 times, and 1,000 times better architectures.”
Chip designers can design chips so they’re faster. But to get to 10 times, 100 times, or 1,000 times better, they will have to change the architecture of their chips, he said.
“I think we are off to a roaring start, but we’re at the beginning so I think there are many more opportunities here,” he said. “And Synopsys is the only company that has really all the pieces underneath for design ready to go.”
Customizing chips for verticals
Above: Custom chips are going to be more popular.
The chip shortage is holding back the industry from generating bigger sales. But the one benefit is that everyone, including those in the car industry, now understands that chips are important. When President Joe Biden holds up a chip and says, “This is infrastructure,” that’s a big advance for general understanding of the industry.
“The takeaway is there is a whole new era in front of us,” de Geus said. “We have cracked the code on what direction to make this happen. And actually we are now delivering results that a year ago I couldn’t have believed … we would have.”
Synopsys has a lot of tapeouts, or finished chip designs, that prove the point.
“Moore’s Law has flattened,” he said. “I think what is happening now is there is suddenly a booster pack that’s coming, and that booster pack is multichip and stacking. It opens the door for much larger numbers of transistors again. And so you add that to the picture, and then you add one more thing, which is every vertical will drive down some additional requirements.”
Automotive chips will have to have their own security, for instance, as well as silicon lifecycle management. So a chip that is in a car for a few years can report to the car that it may be failing and the car knows to tell the driver to get it replaced. This means each segment of an industry, from cars to computers, will demand new kinds of special-purpose chips.
“This is, of course, why we see a wave of AI companies saying ‘Here’s my architecture for these applications,’” de Geus said. “But the reality is that the more you narrow the domain of applicability, the more you can accelerate execution against it. And if the economic value is so high, what’s going to happen is that more and more narrow slices are going to push the chip world to provide more chips.”
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